Intel, the 10-nanometer future with SuperFin

Intel, the 10-nanometer future with SuperFin
Intel has chosen Architecture Day 2020 to present the innovations in the pipeline relating to what at the end of 2018 the company defined "the six pillars of technological innovation": processing, memory, packaging, interconnection, packaging and security.

The news of Intel's Architecture Day 2020

Raja Koduri (Senior Vice President, Chief Architect, General Manager, Architecture, Graphics and Software) talks about it in great detail in the editorial linked to bottom of the article that we invite you to consult for further information. The most important announcement is that concerning the 10 nanometers (or rather 10+) of the SuperFin technology.

The name comes from the merger between "SuperMIM" and "Redefined FinFET". It will already be the basis of the upcoming Tiger Lakes and an iteration for the data center market is planned for the future. Remaining on the Tiger Lake theme, there will also be native support for Thunderbolt 4, PCI Express 4 and USB 4.

Space also for Xe (Xe-LP), architecture related to the graphics sector for solutions video such as DG1. The progress will be appreciable both in terms of performance and in terms of optimization of essential consumption when the intended use is in a portable environment.

Among the topics touched on during the Architecture Day 2020 also Willow Cove and Xe-HP and Xe-HPG (the latter dedicated to gaming), solutions for data centers and software.

Source: Intel

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