Intel, more details on Tiger Lake architecture revealed

Intel, more details on Tiger Lake architecture revealed
Intel started talking in depth about Tiger Lake last week on its Architecture Day 2020, but recently shared more details on the chips coming to Hot Chips 2020. This includes the first image of a Tiger Lake quad-core die and more information about its improved inter-core interconnect bus.

Recall that Tiger Lake processors mark the debut of Intel's 10nm SuperFin transistors, iteration improved of the already existing 10nm. Among the most important benefits are performance improvements of around 15-20% at the same voltage / clock values ​​in some areas and much higher peak frequencies, probably in the 5GHz range for mobile components.

Intel combines these optimized transistors with the new Willow Cove cores, increased cache capacity, optimizations for high speed, Intel Xe LP GPU (offering up to twice the performance of previous generation Intel iGPUs) and support for memory up to LPPDR5-5400 and PCI Express 4.0. Overall, Intel claims Tiger Lake has a “higher than generational level of performance improvement.”

Here we can see the die image Intel shared during its Hot Chips 2020 presentation. Intel did not specifically indicate the various components present within the die, but the large blue area in the lower right corner is probably the Xe LP graphics unit (comprising approximately 33% of the matrix). Intel says this diagram shows a four-core device for illustrative purposes, perhaps suggesting that models with a higher core count may arrive in the future.

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