Intel, Alder Lake-S CPUs will use big.LITTLE design?

Intel, Alder Lake-S CPUs will use big.LITTLE design?
The latest updates of the GNU compiler (as reported by Phoronix) have provided further clues about the future commercialization of Intel CPUs equipped with a hybrid architecture that combines "larger" cores with "smaller" cores.

CPU Alder Lake-S will follow the company's Rocket Lake chips and, although Intel has not yet provided confirmations in this regard, some information has emerged according to which the new processors should be the first made with this hybrid architecture. Indeed, it is said that the Alder Lake chips will be equipped with eight large cores flanked by eight smaller cores in order to offer high-end performance in the most performing cores, while the Atom cores will be used for their high energy efficiency.

The big.LITTLE design debuted in the CPUs of the Santa Clara company with Lakefield, including a Sunny Cove core combined with four Atom Tremont cores. Given that the architecture has already been functionally tested within the ecosystem, its arrival in the desktop world is certainly not impossible.

Updates to the GNU compiler include a list of instructions compatible with both the upcoming Intel Sapphire Ridge chips, intended for data centers, that the Alder Lake desktop chips, although in the latter case there is no support for AVX-512, SIMD instruction that Intel has recently introduced in its desktop CPUs. These instructions are disabled in Lakefield hybrid chips to keep the set consistent between the cores (Atom does not support AVX instructions), thus facilitating the operating system scheduling routines to direct the workloads to the various cores based on the activity required. Therefore, the lack of AVX-512 support for Alder Lake could serve as further proof that Intel will bring its hybrid architecture to desktop PCs.

However, while the lack of support of AVX-512 would seem to indicate a hybrid architecture, in the support matrix of Alder Lake are present, the AVX instructions that are not currently supported by the core Atom Tremont. This means that the core Atom Gracemont next-generation, largely considered to be the core of more “small” used in Alder Lake, could add support for AVX, even if in a limited way, on the line Atom. The roadmap Atom formerly widespread from Intel indicates the increase of the performance vector with Gracemont, making it extremely likely the appearance of these core Atom in Alder Lake.

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